From: user5857@newsgrouper.org.invalid   
      
   Thomas Koenig  posted:   
      
   > Scott Lurndal  schrieb:   
   > > Thomas Koenig  writes:   
   > >>Robert Finch  schrieb:   
   > >>> On 2025-10-29 2:15 p.m., Thomas Koenig wrote:   
   > >>>> Robert Finch  schrieb:   
   > >>>>> Started working on yet another CPU – Qupls4. Fixed 40-bit   
   instructions,   
   > >>>>> 64 GPRs. GPRs may be used in pairs for 128-bit ops. Registers are named   
   > >>>>> as if there were 32 GPRs, A0 (arg 0 register is r1) and A0H (arg 0 high   
   > >>>>> is r33). Sameo for other registers. GPRs may contain either integer or   
   > >>>>> floating-point values.   
   > >>>>   
   > >>>> I understand the temptation to go for more bits :-)  What is your   
   > >>>> instruction alignment?  Bytewise so 40 bits fit, or do you have some   
   > >>>> alignment that the first instruction of a cache line is always aligned?   
   > >>>   
   > >>> The 40-bit instructions are byte aligned. This does add more shifting in   
   > >>> the align stage. Once shifted though instructions are easily peeled off   
   > >>> from fixed positions. One consequence is jump targets must be byte   
   > >>> aligned OR routines could be required to be 32-bit aligned for instance.>   
   > >>   
   > >>That raises an interesting question.  If you want to align a branch   
   > >>target on a 32-bit boundary, or even a cache line, how do you fill   
   > >>up the rest?  If all instructions are 40 bits, you cannot have a   
   > >>NOP that is not 40 bits, so there would need to be a jump before   
   > >>a gap that is does not fit 40 bits.   
   > >   
   > > iCache lines could be a multiple of 5-bytes in size (e.g. 80 bytes   
   > > instead of 64).   
   >   
   > There is a cache level (L2 usually, I believe) when icache and   
   > dcache are no longer separate.  Wouldn't this cause problems   
   > or inefficiencies?   
      
   Consider trying to invalidate an ICache line--this requires looking   
   at 2 DCache lines to see if they, too, need invalidation.   
      
   Consider self-modifying code, the data stream overwrites an instruction,   
   then later the FETCH engine runs over the modified line, but the modified   
   line is 64-bytes of the needed 80-bytes, so you take a hit and a miss on   
   a single fetch.   
      
   It also prevents SNARFing updates to ICache instructions, unless the   
   SNARFed data is entirely retained in a single ICache line.   
      
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