From: anton@mips.complang.tuwien.ac.at   
      
   MitchAlsup  writes:   
   >   
   >anton@mips.complang.tuwien.ac.at (Anton Ertl) posted:   
   >> Intel split AX into AL and AH, similar for BX, CX, and DX, but not for   
   >> SI, DI, BP, and SP.   
   >   
   >{ABCD}X registers were data.   
   >{SDBS}  registers were pointer registers.   
      
   The 8086 is no 68000.  The [BX] addressing mode makes it obvious that   
   that's not the case.   
      
   What is actually the case: AL-DL, AH-DH correspond to 8-bit registers   
   of the 8080, some of AX-DX correspond to register pairs.  SI, DI, BP   
   are new, SP corresponds to the 8080 SP, which does not have 8-bit   
   components.  That's why SI, DI, BP, SP have no low or high   
   sub-registers.   
      
   >Oh and BTW:: using x86-history as justification for an architectural   
   >feature is "bad style".   
      
   I think that we can learn a lot from earlier architectures, some   
   things to adopt and some things to avoid.  Concerning subregisters, I   
   lean towards avoiding.   
      
   That's also another reason to avoid load-and-op and RMW instructions.   
   With a load/store architecture, load can sign/zero extend as   
   necessary, and then most operations can be done at full width.   
      
   >But gains the property that the whole register contains 1 proper value   
   >{range-limited to the container size whence it came} This in turn makes   
   >tracking values easy--in fact placing several different sized values   
   >in a single register makes it essentially impossible to perform value   
   >analysis in the compiler.   
      
   I don't think it's impossible or particularly hard for the compiler.   
   Implementing it in OoO hardware causes complications, though.   
      
   - anton   
   --   
   'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'   
     Mitch Alsup,    
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)