From: user5857@newsgrouper.org.invalid   
      
   Robert Finch  posted:   
      
   > Contemplating having conditional branch instructions branch to a target   
   > value in a register instead of using a displacement.   
   >   
   > I think this has about the same code density as having a branch to a   
   > displacement from the IP.   
   >   
   > Using a fused compare-and-branch instruction for Qupls4 there is not   
   > enough room in the instruction for a large branch displacement (10   
   > bits). So, my thought is to branch to a register value instead.   
   > There is already an add-to-instruction-pointer instruction that can be   
   > used to generate relative addresses.   
      
   The VEC instruction (My 66000) provides a register that is used for   
   the address of the top of the loop and the address of the VEC inst   
   itself. So, when running in the loop, the LOOP instruction branches   
   to the register value, and when taking an exception in the loop,   
   the register leads back to the VEC instruction for after the excpt   
   has been performed.   
      
   > By moving the register load outside of a loop, the dynamic instruction   
   > count can be reduced. I think this solution is a bit better than having   
   > compare and branch as two separate instructions, or having an extended   
   > constant added to the branch instruction.   
      
   VEC-{ }-LOOP always saves at least 1 instruction per iteration.   
      
   > One gotcha may be that the branch target needs to be predicted as it   
   > cannot be calculated earlier in the pipeline.   
      
   VEC does its own predictions. LOOP does not overrun the loop-count,   
   so loop termination is not a pipeline flush.   
      
   > The 10-bit displacement format could also be supported, but it is yet   
   > another branch instruction format. I may leave holes in the instruction   
   > set for future support, but I think it is best to start with just a   
   > single format.   
   >   
   > Code:   
   > AIPSI R3,1234	; add displacement to IP and store in R3 (hoist-able)   
      
        LDA   Rd,[IP,displacement]   
      
   > BLT R1,R2,R3		; branch to R3 if R1 < R2   
   >   
   > Versus:   
   > CMP R3,R1,R2   
   > BLT R3,displacement   
      
   But if you create "R3" from your VEC instruction, you KNOW that   
   the compiler is only allowed to use "r3" as a branch target, and   
   that "R3" is static over the duration of the loop, so you can get   
   the reservation stations moving faster/easier.   
      
   I have a "special" RS for the VEC-LOOP brackets.   
      
   >   
      
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