From: robfi680@gmail.com   
      
   On 2025-11-03 1:47 p.m., Thomas Koenig wrote:   
   > Robert Finch  schrieb:   
   >> Contemplating having conditional branch instructions branch to a target   
   >> value in a register instead of using a displacement.   
   >>   
   >> I think this has about the same code density as having a branch to a   
   >> displacement from the IP.   
   >   
   > Should be possible.  A question is if you want to have a special   
   > register for that (like POWER's link register), tell the CPU   
   > what the target is (like VEC in My66000) or just use a general   
   > purpose register with a general-purpose instruction.   
   >   
   >> Using a fused compare-and-branch instruction for Qupls4   
   >   
   > Is that the name of your architecture, or an instruction?  (That   
   > may have been mentioned upthread, in that case I don't remember).   
      
   That was the name of the architecture, but I am being fickle and   
   scrapping it, restarting with the Qupls2024 architecture innovated to   
   Qupls2026.   
      
   >   
   >> there is not   
   >> enough room in the instruction for a large branch displacement (10   
   >> bits). So, my thought is to branch to a register value instead.   
   >> There is already an add-to-instruction-pointer instruction that can be   
   >> used to generate relative addresses.   
   >   
   > That makes sense.   
      
   Using 48-bit instructions now, so there is enough room for an 18-bit   
   displacement. Still having branch to register as well.>   
   >> By moving the register load outside of a loop, the dynamic instruction   
   >> count can be reduced. I think this solution is a bit better than having   
   >> compare and branch as two separate instructions, or having an extended   
   >> constant added to the branch instruction.   
   >   
   > Are you talking about a normal loop condition or a jump out of   
   > a loop?   
   >   
   Any loop condition that needs a displacement constant. The constant   
   being loaded into a register.   
      
   >> One gotcha may be that the branch target needs to be predicted as it   
   >> cannot be calculated earlier in the pipeline.   
   >   
   > If you use a link register or a special instruction, the CPU could   
   > do that.   
   >   
   >> The 10-bit displacement format could also be supported, but it is yet   
   >> another branch instruction format. I may leave holes in the instruction   
   >> set for future support, but I think it is best to start with just a   
   >> single format.   
   >>   
   >> Code:   
   >> AIPSI R3,1234	; add displacement to IP and store in R3 (hoist-able)   
   >> BLT R1,R2,R3		; branch to R3 if R1 < R2   
   >>   
   >> Versus:   
   >> CMP R3,R1,R2   
   >> BLT R3,displacement   
   >   
      
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