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   comp.arch      Apparently more than just beeps & boops      131,241 messages   

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   Message 130,133 of 131,241   
   Thomas Koenig to MitchAlsup   
   Re: Tonights Tradeoff   
   05 Nov 25 07:13:46   
   
   From: tkoenig@netcologne.de   
      
   MitchAlsup  schrieb:   
   >   
   > Thomas Koenig  posted:   
   >   
   >> Terje Mathisen  schrieb:   
   >>   
   >> > I still think the IBM DFP people did an impressively good job packing   
   >> > that much data into a decimal representation. :-)   
   >>   
   >> Yes, that modulo 1000 packing is quite clever.  It is relatively   
   >> cheap to implement in hardware (which is the point, of course).   
   >> Not sure how easy it would be in software.   
   >   
   > Brain dead easy: 1 table of 1024 entries each 12-bits wide,   
   >                  1 table of 4096 entries each 10-bits wide,   
   > isolate the 10-bit field, LD the converted value.   
   > isolate the 12-bit field, LD the converted value.   
      
   I played around with the formulas from the POWER manual a bit,   
   using Berkeley abc for logic optimization, for the conversion   
   of the packed modulo 1000 to three BCD digits.   
      
   Without spending too much effort, I arrived at four gate delays   
   (INV -> OAI21 -> NAND2 -> NAND2) with a total of 37 gates optimizing   
   for speed, or five gate delays optimizing for space.   
      
   I strongly suspect that IBM is doing something similar :-)   
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