From: user5857@newsgrouper.org.invalid
Robert Finch posted:
> On 2025-11-05 1:47 a.m., Robert Finch wrote:
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> I am now modifying Qupls2024 into Qupls2026 rather than starting a
> completely new ISA. The big difference is Qupls2024 uses 64-bit
> instructions and Qupls2026 uses 48-bit instructions making the code 25%
> more compact with no real loss of operations.
>
> Qupls2024 also used 8-bit register specs. This was a bit of overkill and
> not really needed. Register specs are reduced to 6-bits. Right-away that
> reduced most instructions eight bits.
4 register specifiers: check.
> I decided I liked the dual operations that some instructions supported,
> which need a wide instruction format.
With 48-bits, if you can get 2 instructions 50% of the time, you are only
12% bigger than a 32-bit ISA.
> One gotcha is that 64-bit constant overrides need to be modified. For
> Qupls2024 a 64-bit constant override could be specified using only a
> single additional instruction word. This is not possible with 48-bit
> instruction words. Qupls2024 only allowed a single additional constant
> word. I may maintain this for Qupls2026, but that means that a max
> constant override of 48-bits would be supported. A 64-bit constant can
> still be built up in a register using the add-immediate with shift
> instruction. It is ugly and takes about three instructions.
It was that sticking problem of constants that drove most of My 66000
ISA style--variable length and how to encode access to these constants
and routing thereof.
Motto: never execute any instructions fetching or building constants.
> I could reduce the 64-bit constant build to two instructions by adding a
> load-immediate instruction.
May I humbly suggest this is the wrong direction.
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* Origin: you cannot sedate... all the things you hate (1:229/2)
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