From: tkoenig@netcologne.de   
      
   MitchAlsup  schrieb:   
   >   
   > Thomas Koenig  posted:   
   >   
   >> MitchAlsup  schrieb:   
   >> >   
   >> > Thomas Koenig  posted:   
   >> >   
   >> >> Terje Mathisen  schrieb:   
   >> >>   
   >> >> > I still think the IBM DFP people did an impressively good job packing   
   >> >> > that much data into a decimal representation. :-)   
   >> >>   
   >> >> Yes, that modulo 1000 packing is quite clever.  It is relatively   
   >> >> cheap to implement in hardware (which is the point, of course).   
   >> >> Not sure how easy it would be in software.   
   >> >   
   >> > Brain dead easy: 1 table of 1024 entries each 12-bits wide,   
   >> >                  1 table of 4096 entries each 10-bits wide,   
   >> > isolate the 10-bit field, LD the converted value.   
   >> > isolate the 12-bit field, LD the converted value.   
   >>   
   >> I played around with the formulas from the POWER manual a bit,   
   >> using Berkeley abc for logic optimization, for the conversion   
   >> of the packed modulo 1000 to three BCD digits.   
   >>   
   >> Without spending too much effort, I arrived at four gate delays   
   >> (INV -> OAI21 -> NAND2 -> NAND2) with a total of 37 gates optimizing   
   >> for speed, or five gate delays optimizing for space.   
   >   
   > Since the gates hang off flip-flops, you don't need the inv gate   
   > at the front. Flip-flops can easily give both true and complement   
   > outputs.   
      
   Agreed.  Unfortunately, I have a hard time (i.e. "have not managed")   
   convincing abc that both signals are available, and assert that   
   exactly one of them is 1 at any given time, without completely   
   blowing up the optimization routines.  It also does not handle   
   external don't cares.  But as I use it purely to play around with   
   things, that is not too bad :-)   
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