From: user5857@newsgrouper.org.invalid
Robert Finch posted:
> On 2025-11-05 4:21 p.m., MitchAlsup wrote:
> >
> > Robert Finch posted:
> >
> >> Qupls2026 currently supports 48-bit inline constants. I am debating
> >> whether to support 89 and 130-bit inline constants as well. Constant
> >> sizes increase by 41-bits due to the 48-bit instruction word size. The
> >> larger constants would require more instruction words to be available to
> >> be processed in decode. Not sure if it is even possible to pass a
> >> constant larger than 64-bits in the machine.
> >>
> >> I just realized that constant operand routing was already in Qupls, I
> >> had just not specifically identified it. The operand routing bits are
> >> just moved into a postfix instruction word rather than the first
> >> instruction word. This gives more bits available in the instruction
> >> word. Rather than burn a couple of bits in every R3 type instruction,
> >> another couple of opcodes are used to represent constant extensions.
> >>
> > My 66000 ISA has OpCodes in the range {I.major >= 8 && I.major < 24}
> > that can supply constants and perform operand routing. Within this
> > range; instruction<8:5> specify the following table:
> >
> > 0 0 0 0 +Src1 +Src2
> > 0 0 0 1 +Src1 -Src2
> > 0 0 1 0 -Src1 +Src2
> > 0 0 1 1 -Src1 -Src2
> > 0 1 0 0 +Src1 +imm5
> > 0 1 0 1 +Imm5 +Src2
> > 0 1 1 0 -Src1 -Imm5
> > 0 1 1 1 +Imm5 -Src2
> > 1 0 0 0 +Src1 Imm32
> > 1 0 0 1 Imm32 +Src2
> > 1 0 1 0 -Src1 Imm32
> > 1 0 1 1 Imm32 -Src2
> > 1 1 0 0 +Src1 Imm64
> > 1 1 0 1 Imm64 +Src2
> > 1 1 1 0 -Src1 Imm64
> > 1 1 1 1 Imm64 -Src2
> >
> What happens if one tries to use an unsupported combination?
For 2-operands and 3-operand instructions, they are all present.
For 1-Operand instructions, only the ones targeting Src2 are
available and if you use one not allowed you take an OPERATION
exception.
> > Here we have access to {5, 32, 64}-bit constants, 16-bit constants
> > come from different OpCodes.
> >
> > Imm5 are the register specifier bits: range {-31..31} for integer and
> > logical, range {-15.5..15.5} for floating point.
> I just realized that Qupls2026 does not accommodate small constants very
> well except for a few instructions like shift and bitfield instructions
> which have special formats. Sure, constants can be made to override
> register specs, but they take up a whole additional word. I am not sure
> how big a deal this is as there are also immediate forms of instructions
> with the constant encoded in the instruction, but these do not allow
> operand routing. There is a dedicated subtract from immediate
> instruction. A lot of other instructions are commutative, so operand
> routing is not needed.
1< Qupls has potentially 25, 48, 89 and 130-bit constants. 7-bit constants
> are available for shifts and bitfield ops. Leaving the 130-bit constants
> out for now. They may be useful for 128-bit SIMD against constant operands.
>
> The constant routing issue could maybe be fixed as there are 30+ free
> opcodes still. But there needs to be more routing bits with three source
> operands. All the permutations may get complicated to encode and allow
> for in the compiler. May want to permute two registers and a constant,
> or two constants and a register, and then three or four different sizes.
Out of the 64-slot Major OpCode space, 23-clost are left over, 6-reserved
in perpetuity to catch random jumps into integer or fp data.
> Qupls strives to be the low-cost processor.
My 66000 strives to be the low-instruction-count processor.
But remember, ISA is only the first 1/3rd of an architecture.
--- SoupGate-Win32 v1.05
* Origin: you cannot sedate... all the things you hate (1:229/2)
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