From: anton@mips.complang.tuwien.ac.at
Robert Finch writes:
>Finding it too difficult to support 128-bit operations using high, low
>register pairs. Getting the reservation stations to pair up the
>registers seems a bit scary. It would be much simpler to just have
>128-bit registers and it appears as if it may not be any more logic.
If you want to support 128-bit operations, using 128-bit registers
certainly is the way to go. Note how AMD used to split 128-bit SSE
operations into 64-bit parts on 64-bit registers in the K8, split
256-bit AVX operations into 128-bit parts on 128-bit registers in Zen,
but they went away from that: In Zen4 512-bit operations are performed
in 256-bit-pieces, but the registers are 512 bits wide.
However, the point of carry bits or Mitch Alsup's CARRY is not 128-bit
operations, but multi-precision, which can be 256-bit for some crypto,
4096 bits for other crypto, or billions of bits for the stuff that
Alexander Yee is doing.
>Sparc v9 died?
Oracle has discontinued SPARC development in 2017, Fujitsu has
announced in 2016 that they switch to ARM A64. Both Oracle and
Fujitsu released their last new SPARC CPU in 2017. Fujitsu has
released the ARM A64-based A64FX in 2019. The Leon4 (2017 according
to ) and Leon5
(2019) implement SPARC v8, not v9.
The MCST-R2000 (2018) implements SPARC v9, but will it have a
successor? And even if it has a successor, will it be available in
relevant numbers? MCST is not married to SPARC, despite their name;
they have worked on Elbrus 2000 implementations as well; Elbrus 2000
supports Elbrus VLIW and "Intel x86" instruction sets, and new models
were released in 2018, 2021, and 2025, so MCST now seems to focus on
that.
- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup,
--- SoupGate-Win32 v1.05
* Origin: you cannot sedate... all the things you hate (1:229/2)
|
