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   comp.arch      Apparently more than just beeps & boops      131,241 messages   

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   Message 130,308 of 131,241   
   MitchAlsup to All   
   Re: Multi-precision addition and archite   
   17 Nov 25 18:41:19   
   
   From: user5857@newsgrouper.org.invalid   
      
   Robert Finch  posted:   
      
   > On 2025-11-16 1:36 p.m., MitchAlsup wrote:   
   > > -------------------------------   
   > >   
   > > During its "life" the bits used in CARRY are simply another feedback   
   > > path on the data-path. Afterwards, carry is written once. CARRY also   
   > > gets written when an exception is taken.   
   > >   
   > >>   
   > >> - anton   
   >   
   > These posts have inspired me to keep working on the ISA. I am on a   
   > simplification mission.   
   >   
   > The CARRY modifier is just a substitute for not having r3w2 port   
   > instructions directly in the ISA. Since Qupls ISA has room to support   
   > some r3w2 instructions directly there is no need for CARRY, much as I   
   > like the idea.   
      
   That is correct at the 95% level.   
      
   > While not using a carry flag in the register, there is still a   
   > capabilities bit, overflow bit and pointer bit plus four user assigned   
   > bits. I decided to just have 72-bit register store and load instructions   
   > along with the usual 8,16,32 and 64.   
   >   
   > Finding it too difficult to support 128-bit operations using high, low   
   > register pairs. Getting the reservation stations to pair up the   
   > registers seems a bit scary.   
      
   It IS scary and hard and tricky to get right.   
      
   >                              It would be much simpler to just have   
   > 128-bit registers and it appears as if it may not be any more logic. The   
   > benefit of using register pairs is the internal busses need only be   
   > 64-bits then.   
      
   Almost exactly what we did in Mc 88120 when facing the same problem.   
   Except we kept the 32-bit model and had register files 2 registers   
   tall {even, odd},{odd even} so any register specifier would simply   
   read out the status and values of both registers and then let the   
   stations handle the insundry problems.   
      
   > Sparc v9 died?   
      
   What was the last year SPARC sold more than 100,000 CPUs ??   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)   

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