From: anton@mips.complang.tuwien.ac.at   
      
   MitchAlsup  writes:   
   >   
   >anton@mips.complang.tuwien.ac.at (Anton Ertl) posted:   
   >> There is no need to dump the rename state to memory, not for SPARC nor   
   >> for anything else.  It's only microarchitectural.   
   >   
   >It does need to be checkpointed if/when going OoO.   
      
   You do register renaming in order to go OoO, so OoO is a given.   
   Unless Robert Finch meant the register windowing, but I don't think   
   so.   
      
   And yes, the rename state needs to be checkpointed in order to restore   
   it when recovering from a branch misprediction or the like.  But these   
   checkpoints are also microarchitectural and must not reach   
   architectural memory.   
      
   >>                           With 32 architected registers and 257-512   
   >> physical registers that's 32*9 bits = 288 bits per RAT; with the 136   
   >> architected registers of SPARC, and again <=512 physical registers,   
   >> that would be 1224 bits per RAT.   
   >   
   >Register files with more than 128 entries become big and especially SLOW.   
      
   The 280 physical integer and 332 physical FP registers of Raptor Cove   
   have not prevented it from reaching 6.2GHz.  Zen5 also reaches pretty   
   high clocks with its 384 physical FP registers.   
      
   - anton   
   --   
   'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'   
     Mitch Alsup,    
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)