[continued from previous message]   
      
   >> Finding it too difficult to support 128-bit operations using high, low   
   >> register pairs. Getting the reservation stations to pair up the   
   >> registers seems a bit scary. It would be much simpler to just have   
   >> 128- bit registers and it appears as if it may not be any more logic.   
   >> The benefit of using register pairs is the internal busses need only   
   >> be 64- bits then.   
   >>   
   >   
   > I went with pairs, but I guess maybe pairs are a lot easier for in-order   
   > than OoO.   
      
   I have gone with quads now. It is faked by translating one ISA   
   instruction into four micro-ops doing 64-bit ops. It could go with pairs   
   too in the same manner. The number of registers was upped to 128 so   
   there can be 32x256 bit SIMD registers.   
      
   Shelved the 128-bit ops for now.   
   >   
   >> Sparc v9 died?   
   >>   
   >   
   > Pretty sure SPARC is good and dead at this point...   
   >   
   > Many others in this space are not far behind.   
   >   
   > Basically, anything remaining needs to compete against ARM and RISC-V   
   > (the latter of which making an unexpectedly rapid rise in mind-share and   
   > prominence...).   
   >   
   >   
   I am still waiting to see what else shows up.   
      
   Is the need for backwards compatibility killing things as technology has   
   improved? There seems to be a lot more known good/bad approaches making   
   me think that the lifetime of newer designs could be longer.   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)