[continued from previous message]   
      
   instruction is a common recurrence.   
      
   >                                         I'd not seen an instruction like   
   > that. It is almost like a byte map. I can see how it could be done.   
   > Another instruction to add to the ISA. My compiler does not do such a   
   > nice job of packing the register moves together though.   
      
   Your instruction size can support such a thing, mine would be difficult.   
      
   > >> For context switching a whole bunch of load / store instructions are   
   > >> used. There is context switching in only a couple of places.   
   > >   
   > > I use a cache-model for thread-state {program-status-line and the   
   > > register file}.   
   > >   
   > > The high level simulator, leaves all of the context in memory without   
   > > loading it or storing it. Thus this serves as a pipeline Oracle so if   
   > > the OoO pipeline makes a timing error, the Oracle stops the thread in   
   > > its tracks.   
   > >   
   > > Thus::   
   > >   
   > >       .   
   > >       .   
   > >       -----interrupt detected   
   > >            . change CS (cs--)         <---   
   > >            . access threadState[cs]   
   > >            . t->ip = dispatcher   
   > >            . t->reg[0] = why   
   > >            dispatcher in control   
   > >                 .   
   > >                 .   
   > >                 .   
   > >                 RET   
   > >            SVR   
   > >       .   
   > >       .   
   > >   
   > > In your typical interrupt/exception control transfers, there is   
   > > no code to actually switch state. Just like there is no code to   
   > > switch a cache line that takes a miss.   
   >   
   > The My 66000 hardware takes care of it automatically? Interrupts push   
   > and pop context in my system.   
      
   Yes, context switching is automatic and re-entrant. Whereas exceptions   
   walk up the privilege stack, interrupts go directly to the specified   
   context on the stack. So, you could be operating at high privilege   
   and low priority, only to get interrupted by lower privilege at higher   
   priority.   
      
   > > (*) The cs-- is all that is necessary to change from one Thread State   
   > >      to another in its entirety.   
   > >   
   > >>>> I think the SP should be identified as PUSH / POP would be the only   
   > >>>> instructions assuming the SP register. Otherwise any register could be   
   > >>>> chosen by the compiler.   
   > >>>   
   > >>> I started with that philosophy--and begrudgingly went away from it as   
   > >>> a) the compiler took form   
   > >>> b) we started adding instructions to ISA to remove instructions from   
   > >>>      code footprint.   
   > >>   
   >   
      
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