[continued from previous message]   
      
   1 counter, specifies which events it counts,...   
      
   When the CR is accessed as a multiple, the counters themselves are   
   accessed. It is easy to LDM all 8 counters in a single instruction,   
   or to move all 8 counters with an MM instruction,...   
   {Yes, I remember Scott Lundal dislikes this access structure}   
      
   When Guest OS grants R-- access the counters can be red by application   
   but not modified, so readability and writability are independently   
   controllable.   
      
   As far as performance counters are concerned, each "major resource"   
   has a set of counters. A Core consists of 4 major resources and   
   thus has 32-performance counters. There is a list of 36-envets a   
   core {Fetch-Execute} counts,  a list of 21 events L1 cache counts,   
   a list 25-events the L2 cache counts, and a final list of 15 events   
   the Interconnect block counts.   
      
   Further out, {L3==LLC, DRAM, HostBridge, PCIeRoot, and individual   
   PCIe trees} each have their own sets of counters.   
      
   Yes the counter are still very HW centric--sorry Nick--but it is   
   HW events that the performance counters count.   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)