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   comp.arch      Apparently more than just beeps & boops      131,241 messages   

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   Message 130,438 of 131,241   
   Anton Ertl to David Brown   
   Re: Memory ordering (Re: Multi-precision   
   05 Dec 25 14:37:57   
   
   From: anton@mips.complang.tuwien.ac.at   
      
   David Brown  writes:   
   >"volatile" /does/ provide guarantees - it just doesn't provide enough   
   >guarantees for multi-threaded coding on multi-core systems.  Basically,   
   >it only works at the C abstract machine level - it does nothing that   
   >affects the hardware.  So volatile writes are ordered at the C level,   
   >but that says nothing about how they might progress through storage   
   >queues, caches, inter-processor communication buses, or whatever.   
      
   You describe in many words and not really to the point what can be   
   explained concisely as: "volatile says nothing about memory ordering   
   on hardware with weaker memory ordering than sequential consistency".   
   If hardware guaranteed sequential consistency, volatile would provide   
   guarantees that are as good on multi-core machines as on single-core   
   machines.   
      
   However, for concurrent manipulations of data structures, one wants   
   atomic operations beyond load and store (even on single-core systems),   
   and I don't think that C with just volatile gives you such guarantees.   
      
   - anton   
   --   
   'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'   
     Mitch Alsup,    
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)   

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