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   comp.arch      Apparently more than just beeps & boops      131,241 messages   

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   Message 130,441 of 131,241   
   Robert Finch to All   
   Re: Multi-precision addition and archite   
   06 Dec 25 00:40:11   
   
   From: robfi680@gmail.com   
      
   Tradeoffs bypassing r0 causing more ISA tweaks.   
      
   It is expensive to bypass r0. To truly bypass it, it needs to be   
   bypassed in a couple of dozen places which really drives up the LUT   
   count. Removing the bypassing of r0 from the register file shaved 1000   
   LUTs off the design. This is no real loss as most instructions can   
   substitute small constants for register values.   
      
   Decided to go PowerPC style with bypassing of r0 to zero. R0 is bypassed   
   to zero only in the agen units. So, the bypass is only in a couple of   
   places. Otherwise r0 can be used as an ordinary register. Load / store   
   instructions cannot use r0 as a GPR then, but it works for the PowerPC.   
      
   I hit this trying to decide where to bypass another register code to   
   represent the instruction pointer. In that case I think it may be better   
   to go RISCV style and just add an instruction to add the IP to a   
   constant and place it in a register. The alternative might be to   
   sacrifice a bit of displacement to indicate IP relative addressing.   
      
   Anyone got a summary of bypassing r0 in different architectures?   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)   

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