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   comp.arch      Apparently more than just beeps & boops      131,241 messages   

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   Message 130,442 of 131,241   
   Anton Ertl to Robert Finch   
   Re: Multi-precision addition and archite   
   06 Dec 25 07:26:24   
   
   From: anton@mips.complang.tuwien.ac.at   
      
   Robert Finch  writes:   
   >Tradeoffs bypassing r0 causing more ISA tweaks.   
   >   
   >It is expensive to bypass r0. To truly bypass it, it needs to be   
   >bypassed in a couple of dozen places which really drives up the LUT   
   >count.   
      
   My impression is that modern implementations deal with this kind of   
   stuff at decoding or in the renamer.  That should reduce the number of   
   places where it is special-cased to one, but it means that the uops   
   have to represent 0 in some way.  One way would be to have a physical   
   register that is 0 and that is never allocated, but if your   
   microarchitecture needs a reduction of actual read ports (compared to   
   potential read ports), you may prefer a different representation of 0   
   in the uops.   
      
   - anton   
   --   
   'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'   
     Mitch Alsup,    
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)   

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