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   comp.arch      Apparently more than just beeps & boops      131,241 messages   

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   Message 130,443 of 131,241   
   Robert Finch to Anton Ertl   
   Re: Multi-precision addition and archite   
   06 Dec 25 05:13:01   
   
   From: robfi680@gmail.com   
      
   On 2025-12-06 2:26 a.m., Anton Ertl wrote:   
   > Robert Finch  writes:   
   >> Tradeoffs bypassing r0 causing more ISA tweaks.   
   >>   
   >> It is expensive to bypass r0. To truly bypass it, it needs to be   
   >> bypassed in a couple of dozen places which really drives up the LUT   
   >> count.   
   >   
   > My impression is that modern implementations deal with this kind of   
   > stuff at decoding or in the renamer.  That should reduce the number of   
   > places where it is special-cased to one, but it means that the uops   
   > have to represent 0 in some way.  One way would be to have a physical   
   > register that is 0 and that is never allocated, but if your   
   > microarchitecture needs a reduction of actual read ports (compared to   
   > potential read ports), you may prefer a different representation of 0   
   > in the uops.   
   >   
   > - anton   
      
   Thanks,   
      
   It should have occurred to me to do this at the decode stage. Constants   
   are decoded and passed along for all register fields in decode. There   
   are only four decoders fortunately.   
      
   Switching the ISA back to having r0 as zero all the time.   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)   

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