From: user5857@newsgrouper.org.invalid   
      
   anton@mips.complang.tuwien.ac.at (Anton Ertl) posted:   
      
   > Robert Finch  writes:   
   > >Tradeoffs bypassing r0 causing more ISA tweaks.   
   > >   
   > >It is expensive to bypass r0. To truly bypass it, it needs to be   
   > >bypassed in a couple of dozen places which really drives up the LUT   
   > >count.   
   >   
   > My impression is that modern implementations deal with this kind of   
   > stuff at decoding or in the renamer.  That should reduce the number of   
   > places where it is special-cased to one, but it means that the uops   
   > have to represent 0 in some way.  One way would be to have a physical   
   > register that is 0 and that is never allocated, but if your   
   > microarchitecture needs a reduction of actual read ports (compared to   
   > potential read ports), you may prefer a different representation of 0   
   > in the uops.   
      
   Another way to implement R0 is to have an AND gate after the Operand   
   flip-flop, and if  was captured is R0, then AND with 0, other-   
   wise AND with 1.   
   >   
   > - anton   
      
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