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   comp.arch      Apparently more than just beeps & boops      131,241 messages   

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   Message 130,452 of 131,241   
   Robert Finch to MitchAlsup   
   Re: Multi-precision addition and archite   
   06 Dec 25 18:33:55   
   
   From: robfi680@gmail.com   
      
   On 2025-12-06 12:29 p.m., MitchAlsup wrote:   
   >   
   > Robert Finch  posted:   
   >   
   >> Tradeoffs bypassing r0 causing more ISA tweaks.   
   >>   
   >> It is expensive to bypass r0. To truly bypass it, it needs to be   
   >> bypassed in a couple of dozen places which really drives up the LUT   
   >> count. Removing the bypassing of r0 from the register file shaved 1000   
   >> LUTs off the design. This is no real loss as most instructions can   
   >> substitute small constants for register values.   
   >   
   > Often the use of R0 as an operand causes the calculation to be degenerate.   
   > That is, R0 is not needed at all.   
   >       ADD   R9,R7,R0        // is a MOV instruction   
   >       AND   R9,R7,R0        // is a CLR instruction   
   >   
   We dont want no degenerating instructions.   
      
   > So, you don't have to treat R0 in bypassing, but as Operand processing.   
   >   
   >> Decided to go PowerPC style with bypassing of r0 to zero. R0 is bypassed   
   >> to zero only in the agen units. So, the bypass is only in a couple of   
   >> places. Otherwise r0 can be used as an ordinary register. Load / store   
   >> instructions cannot use r0 as a GPR then, but it works for the PowerPC.   
   >   
   > AGEN Rbase ==R0 implies Rbase  = IP   
   > AGEN Rindex==R0 implies Rindex = 0   
   >   
   Qupls now follows a similar paradigm.   
     Rbase = r0 bypasses to 0   
     Rindex = r0 bypasses to 0   
     Rbase = r31 bypasses to IP   
   Bypassing r0 for both base and index allows absolute addressing mode.   
   Otherwise r0, r31 are general-purpose regs.   
      
   >> I hit this trying to decide where to bypass another register code to   
   >> represent the instruction pointer. In that case I think it may be better   
   >> to go RISCV style and just add an instruction to add the IP to a   
   >> constant and place it in a register. The alternative might be to   
   >> sacrifice a bit of displacement to indicate IP relative addressing.   
   >>   
   >> Anyone got a summary of bypassing r0 in different architectures?   
   >   
   > These are some of the reasons I went with   
   > a) universal constants   
   > b) R0 is just another GPR   
   > So, R0, gets forwarded just as often (or lack thereof) as any joe-random   
   > register.   
      
   Qupls has IP offset constant loading.   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)   

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