From: already5chosen@yahoo.com
On Sun, 7 Dec 2025 09:30:50 -0000 (UTC)
Thomas Koenig wrote:
> Scott Lurndal schrieb:
>
> > Yes, you can add special instructions. However, the compilers
> > will be unlikely to generate them, thus applications that desired
> > the generation of such an instruction would need to create a
> > compiler extension (like gcc __builtin functions) or inline
> > assembler which would then make the program that uses the
> > capability both compiler specific _and_ hardware specific.
>
> This would likely be hidden in a header, and need only be
> written once (although gcc and clang, for example, are compatible
> in this respecct). And people have been doing this, even for
> microarchitecture specific features, if the need for performance
> gain is large enough.
>
> A primary example is Intel TSX, which is (was?) required by SAP.
>
By SAP HANA, I assume.
Not sure for how long it was true. It sounds very unlikely that it is
still true.
> POWER also had a transactional memory feature, but they messed it
> up for POWER 9 and dropped it for POWER 10 (IIRC); POWER is the
> only other architecture certified to run SAP, so it seems they
> can do without.
>
> Googling around, I also find the "Transactional Memory Extension"
> for ARM datetd 2022, so ARM also appears to see some value in that,
> at least enough to write a spec for it.
>
> > Most extant SMP processors provide a compare and swap operation,
> > which are widely supported by the common compilers that support the
> > C and C++ threading functionality.
>
> It seems there is a market for going beyond compare and swap.
TSX is close to dead.
ARM's TME was announced almost 5 years ago. AFAIK, there were no
implementations. Recently ARM said that FEAT_TME is obsoleted. It sounds
like the whole thing is dead, but there is small chance that I am
misinterpreting.
--- SoupGate-Win32 v1.05
* Origin: you cannot sedate... all the things you hate (1:229/2)
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