[continued from previous message]   
      
   > >>>        esmLOCKstore( fr->next,  tn );   
   > >>>                      return TRUE;   
   > >>>        }   
   > >>>        return FALSE;   
   > >>> }   
   > >>>   
   > >>> So, I guess, you are not talking about what My 66000 cannot do, but   
   > >>> only what other ISAs cannot do.   
   > >>   
   > >> Of course.  It is interesting to speculate about possible features of an   
   > >> architecture like yours, but it is not likely to be available to anyone   
   > >> else in practice (unless perhaps it can be implemented as an extension   
   > >> for RISC-V).   
   > >>   
   > >>>>                                                              Even with a   
   > >>>> single core system you can have pre-emptive multi-threading, or at least   
   > >>>> interrupt routines that may need to cooperate with other tasks on data.   
   > >>>>   
   > >>>>>   
   > >>>>>> and I don't think that C with just volatile gives you such guarantees.   
   > >>>>>>   
   > >>>>>> - anton   
   > >>>>   
   > >>   
   >   
      
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