From: user5857@newsgrouper.org.invalid   
      
   Thomas Koenig  posted:   
      
   > MitchAlsup  schrieb:   
   >   
   > > Many early RISC assemblers were in charge of moving instructions around   
   > > subject to not altering register dependencies and not altering control   
   > > flow dependencies. This allowed those assemblers to move code across   
   > > memory instructions, across long latency calculation instructions,   
   > > branch instructions, including delay slots; and redefine what "program   
   > > order" now is. A bad side effect of exposing the pipeline to SW.   
   >   
   > I never heard of that one.   
   >   
   > Sounds like bad design - that should be done by the compiler,   
   > not the assembler.  It is fine for the compiler to have pipeline   
   > descriptions in the cost model of the CPU under a specific -march   
   > or -mtune flag.   
   >   
   > (Yes, it is preferred that performance should be rather good for   
   > code generated for a generic microarchitecture).   
   >   
   > > We mostly have gotten away from this due to "smart" instruction queueing.   
   >   
   > What is that?   
   >   
   Reservation stations {Value capturing and value free}, Scoreboards,   
   Dispatch stacks, and similar.   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)