From: chris.m.thomasson.1@gmail.com   
      
   On 12/12/2025 2:05 PM, MitchAlsup wrote:   
   >   
   > Thomas Koenig  posted:   
   >   
   >> MitchAlsup  schrieb:   
   >>   
   >>> Many early RISC assemblers were in charge of moving instructions around   
   >>> subject to not altering register dependencies and not altering control   
   >>> flow dependencies. This allowed those assemblers to move code across   
   >>> memory instructions, across long latency calculation instructions,   
   >>> branch instructions, including delay slots; and redefine what "program   
   >>> order" now is. A bad side effect of exposing the pipeline to SW.   
   >>   
   >> I never heard of that one.   
   >>   
   >> Sounds like bad design - that should be done by the compiler,   
   >> not the assembler.  It is fine for the compiler to have pipeline   
   >> descriptions in the cost model of the CPU under a specific -march   
   >> or -mtune flag.   
   >>   
   >> (Yes, it is preferred that performance should be rather good for   
   >> code generated for a generic microarchitecture).   
   >>   
   >>> We mostly have gotten away from this due to "smart" instruction queueing.   
   >>   
   >> What is that?   
   >>   
   > Reservation stations {Value capturing and value free}, Scoreboards,   
   > Dispatch stacks, and similar.   
      
   Iiic, over on the PPC, wrt LL/SC, it was the reservation granule. I   
   think it could be larger that a L2 cache line. So, any interference in   
   that granule could cause LL/SC to fail. This can lead to livelock if the   
   program's data was not aligned and/or padded correctly.   
      
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