From: quadibloc@invalid.invalid   
      
   Given the great popularity of the RISC architecture, I assumed that one of   
   its characteristics, instructions that are all 32 bits in length, produced   
   a great increase in efficiency over variable-length instructions.   
   Therefore, I came up with the idea of using some opcode space for block   
   headers which could contain information about the lengths of instructions,   
   so as to make decoding variable-length instructions fully non-serialized,   
   thus giving me the best of both worlds.   
   However, this involved overhead, and the headers would themselves take   
   time to decode. In any event, all the schemes I came up with were also   
   elaborate and overly complicated.   
   But I have finally realized what I think is the decisive reason why I had   
   been mistaken.   
   Before modern pipelined computers, which have multi-stage pipelines for   
   instruction _execution_, a simple form of pipelining was very common -   
   usually in the form of a three-stage fetch, decode, and execute pipeline.   
   Since the decoding of instructions can be so neatly separated from their   
   execution, and thus performed well in advance of it, any overhead   
   associated with variable-length instructions becomes irrelevant because it   
   essentially takes place very nearly completely in parallel to execution.   
      
   John Savard   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)