From: ThatWouldBeTelling@thevillage.com   
      
   Thomas Koenig wrote:   
   > EricP  schrieb:   
   >   
   >> For a VAX memory read it had to (roughly speaking):   
   >> (1) translate virtual->physical address   
   >> (2) go through the cache (read miss)   
   >> (3) get to the SBI (there is a 1 entry store buffer on cache output)   
   >> (4) negotiate for SBI   
   >> (5) SBI take 2 cycles to transmit control and read address   
   >> (6) memory controller does its thing   
   >> (7) memory controller negotiates for SBI   
   >> (8) memory controller transmits 32B cache line (1 control + 8*4B data   
   clocks)   
   >> (9) cache receives and saves 32B cache line   
   >> (10) cache returns 4B value to 780 core   
   >   
   > The VAX cache line was 8 bytes according to   
   > https://dl.acm.org/doi/pdf/10.1145/357353.357356   
   > ..   
      
   You are correct. I was thinking it was 8 words.   
   (That's a lot of tag overhead for such a small data cache.)   
   So 2*4B data clocks.   
      
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