From: anton@mips.complang.tuwien.ac.at   
      
   John Savard  writes:   
   >Given the great popularity of the RISC architecture, I assumed that one of   
   >its characteristics, instructions that are all 32 bits in length, produced   
   >a great increase in efficiency over variable-length instructions.   
      
   Some RISCs have that, some RISCs have two instruction lengths: 16 bits   
   and 32 bits: IIRC one variant of the IBM 801 (inherited by the ROMP,   
   but then eliminated in Power), one variant of Berkeley RISC, ARM T32,   
   RISC-V with the C extension, and probably others.   
      
   >Before modern pipelined computers, which have multi-stage pipelines for   
   >instruction _execution_, a simple form of pipelining was very common -   
   >usually in the form of a three-stage fetch, decode, and execute pipeline.   
   >Since the decoding of instructions can be so neatly separated from their   
   >execution, and thus performed well in advance of it, any overhead   
   >associated with variable-length instructions becomes irrelevant because it   
   >essentially takes place very nearly completely in parallel to execution.   
      
   It is certainly possible to decode potential instructions at every   
   starting position in parallel, and later select the ones that actually   
   correspond to the end of the previous instruction, but with 16-bit and   
   32-bit instructions this potentially doubles the amount of instruction   
   decoders necessary, plus the circuit for selecting the ones that are   
   at actual instruction starts.  I guess that this is the reason why ARM   
   uses an uop cache in cores that can execute ARM T32.  The fact that   
   more recent ARM A64-only cores have often no uop cache while their   
   A64+T32 predecessors have had one reinforces this idea.   
      
   OTOH, on AMD64/IA-32 Intel's recent E-Cores do not use an uop cache   
   either, but instead the most recent instances have 3 decoders each of   
   which can decode 3 instructions per cycle (i.e., they attempt to   
   decode at many more positions and then select 3 per cycle out of   
   those); so apparently even byte-oriented variable-length encoding can   
   be decoded quickly enough.   
      
   - anton   
   --   
   'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'   
     Mitch Alsup,    
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)