From: monnier@iro.umontreal.ca   
      
   >> Well, Mitch claims average 35 bits per instructions, that means about   
   >> 90% utilization of decoders, so not bad.   
   > His minimum instruction size is 32 bits, but I was going for 16 bits.   
      
   BTW, my understanding of Mitch's design is that this is related to   
   instruction complexity: if you support 16bit instructions, it means you   
   support instructions which presumably don't do very much work because   
   it's hard to express a lot of "work to do" in 16bit.   
      
   Instead, the My 66000 ISA tries to make instructions fatter, so as to   
   reduce the number of instructions rather than the size of each instruction.   
   And the idea is that this applies both to static and to dynamic counts.   
      
   That's why Mitch includes negation and sign-extension directly inside   
   every arithmetic instruction.  The hope is that they don't increase the   
   critical path (in the combinatory logic of a single cycle), or they   
   increase it less than the corresponding decrease in the other critical   
   path (the one in the dataflow graph of instructions).   
      
   Another way to look at it: For the execution of any specific   
   instruction, we spend N1 gate-delays on useful work, N2 gate-delays   
   waiting for the end of the cycle (because the duration of cycle is based   
   on the maximum of all possible N1s), and N3 gate-delays on latching.   
   Fatter instructions are a way to try and reduce N2 and the number of   
   times we pay N3.   
      
   I wish I knew how to make an ISA where the single cycle instructions   
   can perform even more work like two or more dependent additions.   
   [ I mean, I know of ways to do it, but they all tend to increase N2   
     much too much on average.  ]   
      
      
           Stefan   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)