From: user5857@newsgrouper.org.invalid   
      
   Stefan Monnier  posted:   
      
   > >> Well, Mitch claims average 35 bits per instructions, that means about   
   > >> 90% utilization of decoders, so not bad.   
   > > His minimum instruction size is 32 bits, but I was going for 16 bits.   
   >   
   > BTW, my understanding of Mitch's design is that this is related to   
   > instruction complexity: if you support 16bit instructions, it means you   
   > support instructions which presumably don't do very much work because   
   > it's hard to express a lot of "work to do" in 16bit.   
   >   
   > Instead, the My 66000 ISA tries to make instructions fatter, so as to   
   > reduce the number of instructions rather than the size of each instruction.   
   > And the idea is that this applies both to static and to dynamic counts.   
      
   AND more importantly--LATENCY !   
      
   > That's why Mitch includes negation and sign-extension directly inside   
   > every arithmetic instruction.  The hope is that they don't increase the   
   > critical path (in the combinatory logic of a single cycle), or they   
   > increase it less than the corresponding decrease in the other critical   
   > path (the one in the dataflow graph of instructions).   
      
   If your adder has a carry in, my adder has no more gates of delay.   
      
   > Another way to look at it: For the execution of any specific   
   > instruction, we spend N1 gate-delays on useful work, N2 gate-delays   
   > waiting for the end of the cycle (because the duration of cycle is based   
   > on the maximum of all possible N1s), and N3 gate-delays on latching.   
   > Fatter instructions are a way to try and reduce N2 and the number of   
   > times we pay N3.   
      
   Pretty spot on.   
      
   > I wish I knew how to make an ISA where the single cycle instructions   
   > can perform even more work like two or more dependent additions.   
      
   Data-General Nova. However, with a modern RISC-like ISA, there are not   
   enough small-shifts to amortize--except in the memory addressing arena   
   where scaled indexing saves instructions and cycles.   
      
   > [ I mean, I know of ways to do it, but they all tend to increase N2   
   >   much too much on average.  ]   
      
   If you understand My 66000 ISA implementation, you will find that   
   each stage in the pipeline has 1 more gate-of-delay than a typical   
   RISC-V pipeline. Given a 16-gate-delay logical pipeline (21 gates   
   per clock) I lose 5% while gaining 40%. I consider this a good trade-   
   off. With modern wire versus gate delays, I am losing less than 5%   
   while still gaining that 40%. {Hint 1/70% = 140%)   
   >   
   >   
   >         Stefan   
      
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