From: monnier@iro.umontreal.ca   
      
   MitchAlsup [2025-12-28 17:59:02] wrote:   
   > Stefan Monnier  posted:   
   >> I wish I knew how to make an ISA where the single cycle instructions   
   >> can perform even more work like two or more dependent additions.   
   > Data-General Nova. However, with a modern RISC-like ISA, there are not   
   > enough small-shifts to amortize--except in the memory addressing arena   
   > where scaled indexing saves instructions and cycles.   
      
   My thoughts were something along the lines of having fat instructions   
   like a 3-in 2-out 2-op instruction that does:   
      
        Rd1 <= Rs1 OP1 Rs2;   
        Rd2 <= Rs3 OP2 Rd1;   
      
   so your datapath has two ALUs back to back in a single cycle.  And the   
   problem is that it's often hard to find something useful to do in that   
   OP2.  To increase the use of OP2 you need to allow as many combinations   
   of OP1 and OP2 and that quickly bumps into the constraints that OP1+OP2   
   are done in a single cycle, so neither OP1 nor OP2 can usefully be   
   memory memory access or control flow operations.   
      
   Those 2 ALUs would likely lengthen the cycle by significantly more than   
   your single gate-of-delay, so it's important for OP2 to make useful work   
   most of the time, otherwise we just increased the average N2.   
   [ And then there's the impact of 3-in 2-out on the pipeline, and the fact   
     that such a multi-op instruction doesn't fit in 32bit, of course.  ]   
      
      
           Stefan   
      
   --- SoupGate-Win32 v1.05   
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