From: monnier@iro.umontreal.ca   
      
   >> My thoughts were something along the lines of having fat instructions   
   >> like a 3-in 2-out 2-op instruction that does:   
   >>   
   >>      Rd1 <= Rs1 OP1 Rs2;   
   >>      Rd2 <= Rs3 OP2 Rd1;   
   >>   
   >> so your datapath has two ALUs back to back in a single cycle.   
   > SuperSPARC tried this, it does not work "all that well".   
      
   Do you have a reference to that?  I can't see any trace of that in the   
   SPARC ISA, so I assume it was done via instruction fusion instead?   
      
   > One might notice that None of the SPARC generations were anywhere close to   
   > the frequency of the more typical RISCs.   
      
   Hmm... I remember Sun being slower to move to OoO, but in terms of   
   frequency I thought they were mostly on par with other RISCs of the time   
   (and back then, SPARC was one of the top two "typical RISCs", AFAIK).   
      
      
           Stefan   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)