From: user5857@newsgrouper.org.invalid   
      
   Stefan Monnier  posted:   
      
   > >> My thoughts were something along the lines of having fat instructions   
   > >> like a 3-in 2-out 2-op instruction that does:   
   > >>   
   > >>      Rd1 <= Rs1 OP1 Rs2;   
   > >>      Rd2 <= Rs3 OP2 Rd1;   
   > >>   
   > >> so your datapath has two ALUs back to back in a single cycle.   
   > > SuperSPARC tried this, it does not work "all that well".   
   >   
   > Do you have a reference to that?  I can't see any trace of that in the   
   > SPARC ISA, so I assume it was done via instruction fusion instead?   
      
   It is not in ISA, and it is not "like" instruction Fusion, either.   
      
   When a first instruction had a property*, and a second instruction also   
   had a certain property*, they would be issued together into the execution   
   pipeline. The first instruction executes in the first cycle, the second   
   instruction in the second cycle with forwarding of the result of the first   
   to the second.   
      
   Where property ~= 1-cycle integer, no setting of CCs, and a few other   
                     conditions.   
      
   > > One might notice that None of the SPARC generations were anywhere close to   
   > > the frequency of the more typical RISCs.   
   >   
   > Hmm... I remember Sun being slower to move to OoO, but in terms of   
   > frequency I thought they were mostly on par with other RISCs of the time   
   > (and back then, SPARC was one of the top two "typical RISCs", AFAIK).   
      
   S/frequency/performance/g   
      
   >   
   >   
   >         Stefan   
      
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