From: already5chosen@yahoo.com   
      
   On Tue, 30 Dec 2025 21:36:29 GMT   
   MitchAlsup  wrote:   
      
   > BGB  posted:   
   >   
   > >   
   > > Though, the main places where compressed instructions are likely to   
   > > bring meaningful benefit, is on small in-order machines.   
   >   
   > Coincidentally; this is exactly where a fatter-ISA wins big::   
   > compare::   
   >   
   >      LDD    R7,[IP,R3<<3,DISP32]   
   >   
   > 1 instruction, 3 words, 0 wasted registers, cache-hit minimum--against   
   >   
   >      AUPIC  Rt,lo(DISP32)   
   >      SLL    Ri,R3,#3   
   >      ADD    Rt,Rt,hi(DISP32)   
   >      ADD    Rt,Rt,Ri   
   >      LDD    R7,0(Rt)   
   >   
   > 5 instructions, 4 words, 2-wasted registers, 4-cycles+cache hit   
   > minimum.   
   > > Any OoO machine is also likely to have a lot of RAM and a decent   
   > > sized I$, so much of any benefit is likely to go away in this case.   
   > >   
   >   
      
   And where do we have 95% of those small in-order machines? We have them   
   in flash-based micro-controllers, more often than not without I$, more   
   often than not running at higher clock than sustainable without wait   
   states by their program flash with 32-bit data bus. In other words,   
   bottlenecked by instruction fetch before anything else, including   
   decode.   
      
   BGB trained his intuition on soft cores in FPGA, where trade offs are   
   completely different. I am heavy users of soft cores too. But I realize   
   that 32-bit MCU cores outsell soft cores by more than order of   
   magnitude and quite likely by more than 2 orders of magnitude.   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)