From: cr88192@gmail.com   
      
   On 12/30/2025 3:49 PM, Michael S wrote:   
   > On Tue, 30 Dec 2025 21:36:29 GMT   
   > MitchAlsup  wrote:   
   >   
   >> BGB  posted:   
   >>   
   >>>   
   >>> Though, the main places where compressed instructions are likely to   
   >>> bring meaningful benefit, is on small in-order machines.   
   >>   
   >> Coincidentally; this is exactly where a fatter-ISA wins big::   
   >> compare::   
   >>   
   >>       LDD    R7,[IP,R3<<3,DISP32]   
   >>   
   >> 1 instruction, 3 words, 0 wasted registers, cache-hit minimum--against   
   >>   
   >>       AUPIC  Rt,lo(DISP32)   
   >>       SLL    Ri,R3,#3   
   >>       ADD    Rt,Rt,hi(DISP32)   
   >>       ADD    Rt,Rt,Ri   
   >>       LDD    R7,0(Rt)   
   >>   
   >> 5 instructions, 4 words, 2-wasted registers, 4-cycles+cache hit   
   >> minimum.   
   >>> Any OoO machine is also likely to have a lot of RAM and a decent   
   >>> sized I$, so much of any benefit is likely to go away in this case.   
   >>>   
   >>   
   >   
   > And where do we have 95% of those small in-order machines? We have them   
   > in flash-based micro-controllers, more often than not without I$, more   
   > often than not running at higher clock than sustainable without wait   
   > states by their program flash with 32-bit data bus. In other words,   
   > bottlenecked by instruction fetch before anything else, including   
   > decode.   
   >   
      
   Yes, I will not disagree with this.   
      
   This was actually partly the point I was trying to make, just expressed   
   from the other direction.   
      
      
   > BGB trained his intuition on soft cores in FPGA, where trade offs are   
   > completely different. I am heavy users of soft cores too. But I realize   
   > that 32-bit MCU cores outsell soft cores by more than order of   
   > magnitude and quite likely by more than 2 orders of magnitude.   
   >   
      
   I don't see where the disagreement is here, exactly.   
      
      
   I was not saying Compressed instructions don't make sense for   
   microcontrollers, rather, this is the main place they *do* make sense.   
      
   Rather, it on Desktop PC and Server class systems (or, IOW, the ones   
   likely to have OoO processors), is where compressed instructions would   
   likely stop bringing all that much benefit, as the I$ is bigger and RAM   
   is basically unlimited (at least provided your code density isn't IA-64   
   levels of bad).   
      
   So, for your Application Class processors, 32-bit only or 32/64/96 or   
   similar, would likely make more sense.   
      
      
   But, on the other side, say, RV32IMC or similar is a good choice for a   
   microcontroller. But, for a PC or similar, not so much.   
      
      
   So, the point is that it does make sense to design a compressed ISA to   
   optimize around the constraints of small in-order CPUs, as these are the   
   place where compressed instructions are most likely to be "actually useful".   
      
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