From: ThatWouldBeTelling@thevillage.com
Anton Ertl wrote:
> anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:
>> Looking at the "18 RISC-V Compressed ISA V1.9" specification
>
> Someone asked for more and dynamic numbers. This work contains them
> in Section 1.9:
>
> |Table 1.7 lists the standard RVC instructions with the most frequent
> |first, showing the individual contributions of those instructions to
> |static code size and then the running total for three experiments: the
> |SPEC benchmarks for both RV32C and RV64C for the Linux kernel. For
> |RV32, RVC reduces static code size by 24.5% on Dhrystone and 30.9% on
> |CoreMark. For RV64, it reduces static code size by 26.3% on SPECint,
> |25.8% on SPECfp, and 31.1% on the Linux kernel.
> |
> |Table 1.8 ranks the RVC instructions by order of typical dynamic
> |frequency. For RV32, RVC reduces dynamic bytes fetched by 29.2% on
> |Dhrystone and 29.3% on CoreMark. For RV64, it reduces dynamic bytes
> |fetched by 26.9% on SPECint, 22.4% on SPECfp, and 26.11% booting the
> |Linux kernel.
>
> If you want the tables, look at source:
>
>
> - anton
I came across a paper which suggests various changes to the RVC ISA
to improve the compaction rate based on the actual usage.
Things like noting that register a5 is used with ADDI Add Immediate
instruction 40% of the time. You could hard code the a5 into an
opcode and use those bits in the immediate field.
Or hard coding the link register for JAL.
Reduce Static Code Size and Improve RISC-V Compression 2019
https://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-107.pdf
But RVC has been getting 50%+ compression rates since the start in 2011.
Mostly this is fiddling around the edges for an extra 5% or so.
Improving Energy Efficiency and Reducing Code Size with
RISC-V Compressed 2011
https://www2.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-63.pdf
--- SoupGate-Win32 v1.05
* Origin: you cannot sedate... all the things you hate (1:229/2)
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