From: user5857@newsgrouper.org.invalid   
      
   Robert Finch  posted:   
      
   > Have inverted page tables fallen out of favor?   
      
   Not so much as: that "they were never really IN Favor".   
      
   >                                                And how much OS support   
   > is there for them?   
      
   Probably just enough to get buy if you copy an existing IPT.   
      
   > I am thinking about using an inverted page table instead of a   
   > hierarchical page table for the current project. The advantage is that   
   > the entire page table should be able to fit into BRAM on the FPGA. It   
   > should then be possible to eliminate the TLB from the design at perhaps   
   > a small performance cost. It would reduce the LUT cost of the MMU.   
      
   An alternative is for HW to generate a hash address based on faulting   
   VA and make one probe into a 1-16MB TLB stored across the memory hierarchy.   
   If the access matches VA the rest of the data is your PTE. If not, then   
   you trap to SW to refill the memory-TLB. Rational:: if the hashed address   
   is not that bad, and the hash table is large, TLB refills end up at low   
   cost (delay).   
      
   > Translations could work directly from the page table.   
   >   
   > The hash function would select a page table group. Averaging about 1.2   
   > lookups per memory access. Using the ASID xor’d with address bits 20 to   
   > 29 as the hash. 32k entries in the table.   
   >   
   > Using 64kB pages to keep the page table small. 1GB RAM to manage.   
      
   But realistically, a HW table-walker with a bit of internal caching   
   supplemented with a large L2-TLB works fine in practice.   
      
   --- SoupGate-Win32 v1.05   
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