From: paaronclayton@gmail.com   
      
   On 2/3/26 1:03 AM, Robert Finch wrote:   
   > After getting bogged down testing the hash table, I decided to   
   > shelf it for now. And...   
   >   
   > I re-wrote Qupls4 TLB for hierarchical page tables. It is much   
   > cleaner code now. The TLB is taking up only about 600 LUTs and 8   
   > BRAMs now. It is also simpler being only a single level TLB.   
   > Three copies of the TLB would be needed.   
   >   
   > Thinking about adding caching of translation steps to avoid main   
   > memory access.   
      
   If you use huge pages where page table nodes can be larger   
   pages, then you might consider merging the page directory entry   
   and huge PTE cache. This wastes N bits (10 bits for 32-bit PTEs   
   and 4 KiB pages) for the PDE unless huge pages use these bits   
   for additional TLB-managed features (or PDEs are constrained to   
   an N-bit smaller address space, which is awkward). However, such   
   allows entries to be used for both kinds of data (since both   
   have the same index:tag bits). (if I recall correctly x86   
   allowed 4 MiB pages to use a 42-bit address space by using the   
   bits that would otherwise be zero due to 4 MiB huge page   
   alignment. (I think this sharing works better for a modest-sized   
   L2 huge page TLB/PDE cache.)   
      
   This sharing saves a few tag bits compared with hash/rehash TLB   
   for multiple page sizes at the cost of fixed large region   
   caching size (though a hash/rehash TLB could repurpose the 2N   
   bits — N from the tag and N from the translation for huge   
   pages).   
      
   In theory, with rehashing the reduced tag entries could be used   
   for base-sized pages that can be sign extended for the missing   
   bits. Such might be useful as a victim cache, but I suspect such   
   a feature would not be worthwhile.   
      
   With PDE caching, it also becomes possible to use André Seznec's   
   "Don't use the page number but a pointer to it" for TLB tags to   
   compress the tags. (The PDE cache already holds the top virtual   
   address bits [and any ASID], so the small page TLB entries can   
   use a pointer to the PDE cache entry to compress the TLB entry.   
   Unlike Seznec's proposal, this requires reading an extra table,   
   though if the PDE cache used for this compression is also a   
   large page TLB then parallel access might be desired anyway.)   
      
   Replacement decisions might be more complicated with support for   
   different entry types.   
      
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