From: terje.mathisen@tmsw.no   
      
   MitchAlsup wrote:   
   >   
   > Robert Finch  posted:   
   >   
   >> On 2026-02-15 7:14 a.m., David Brown wrote:   
   >>> On 15/02/2026 09:58, Robert Finch wrote:   
   >>>   
   >>>> I wonder how difficult it would be to implement a parallel tester in   
   >>>> an FPGA. It looks simple enough and there are hundreds of DSP blocks   
   >>>> available to use. Could test in blocks of hundreds of numbers at a time.   
   >>>> Running at 100 MHz * 200 tests at a time = how long to get to 2^71?   
   >>>>   
   >>>   
   >>> One of the nice things about this is that you don't need DSP blocks - it   
   >> Yeah, I figured that out after coding. 3n+1 = n+n+n+1   
   >   
   > 3n+1 = (n<<1)+n+1   
   >   
   > one add with carry in and n gets wired in directly and also shifted   
   > up by 1 (no logic shifter).   
      
   Even better:   
      
   (3n+1)/2 = n + (n>>1) + 1   
      
   I.e two iterations for the cost of one.   
      
   Terje   
      
   --   
   -    
   "almost all programming can be viewed as an exercise in caching"   
      
   --- SoupGate-Win32 v1.05   
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