From: user5857@newsgrouper.org.invalid   
      
   anton@mips.complang.tuwien.ac.at (Anton Ertl) posted:   
      
   > jgd@cix.co.uk (John Dallman) writes:   
   > [some unattributed source writes:]   
   ----------------   
   > Actually, other architectures also added prefetching instructions for   
   > dealing with that problem.  All I have read about that was that there   
   > were many disappointments when using these instructions.  I don't know   
   > if there were any successes, and how frequent they were compared to   
   > the disappointments.  So I don't see that IA-64 was any different from   
   > other architectures in that respect.   
      
   If there had been any significant successes, you would have heard about them.   
      
   -------------------------------   
   > Otherwise what kind of common code do we have that is   
   > memory-dominated?  Tree searching and binary search in arrays come to   
   > mind, but are they really common, apart from programming classes?   
      
   Array and Matrix scientific codes with datasets bigger than cache.   
      
   >----------------------------   
   > I have certainly read about interesting results for binary search (in   
   > an array) where the branching version outperforms the branchless   
   > version because the branching version speculatively executes several   
   > followup loads, and even in unpredictable cases the speculation should   
   > be right in 50% of the cases, resulting in an effective doubling of   
   > memory-level parallelism (but at a much higher cost in memory   
   > subsystem load).  But other than that, I don't see that speculative   
   > execution helps with memory latency.   
      
   At the cost of opening the core up to Spectré-like attacks.   
   ------------------------   
   > The instruction format makes no difference.  Having so many registers   
   > may have mad it harder than otherwise, but SPARC also used many   
   > registers, and we have seen OoO implementations (and discussed them a   
   > few months ago).  The issue is that speculative execution and OoO   
   > makes all the EPIC features of IA-64 unnecessary, so if they cannot do   
   > a fast in-order implementation of IA-64 (and they could not), they   
   > should just give up and switch to an architecture without these   
   > features, such as AMD64.  And Intel did, after a few years of denying.   
   > The remainder of IA-64 was just to keep it alive for the customers who   
   > had bought into it.   
      
   IA-64 was to prevent AMD (and others) from clones--that is all. Intel/HP   
   would have had a patent wall 10 feet tall.   
      
   It did not fail by being insufficiently protected, it failed because it   
   did not perform.   
   -----------------   
   > For a few cases, they have.  But the problem is that these cases are   
   > also vectorizable.   
   >   
   > Their major problem was that they did not get enough ILP from   
   > general-purpose code.   
   >   
   > And even where they had enough ILP, OoO CPUs with SIMD extensions ate   
   > their lunch.   
      
   And that should have been the end of the story. ... Sorry Ivan.   
      
   >   
   > - anton   
      
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