From: already5chosen@yahoo.com
On Sun, 22 Feb 2026 14:48:13 -0500
EricP wrote:
> Michael S wrote:
> > On Sat, 21 Feb 2026 15:39:42 -0500
> > EricP wrote:
> >
> >> Robert Finch wrote:
> >>> On 2026-02-19 5:10 a.m., Michael S wrote:
> >>>
> >>>> If it is smaller than Kintex KU5P then I'd strongly suspect that
> >>>> you didn't clean out all mistakes.
> >>>>
> >>>>
> >>>>
> >>> There could be more mistakes for sure. But I am sure the lowest
> >>> level core works. It seemed to in simulation. I made a slight mod
> >>> to it since I tested it last, checking n < startn.
> >>> Counts are not used so the logic would be stripped out, but its
> >>> good for verification.
> >>>
> >>> 1 Core is:
> >>>
> >>> module Collatz_conjecture(rst, clk, startn, count, done);
> >>> input rst;
> >>> input clk;
> >>> input [127:0] startn;
> >>> output reg [127:0] count;
> >>> output reg done;
> >>> reg [127:0] n;
> >>>
> >>> always_ff @(posedge clk)
> >>> if (rst) begin
> >>> n <= startn;
> >>> count <= 0;
> >>> done <= FALSE;
> >>> end
> >>> else begin
> >>> if (!done) begin
> >>> if (~n[0])
> >>> n <= n >> 2'd1;
> >>> else
> >>> n <= n+n+n+1;
> >>> if (n < startn)
> >>> done <= TRUE;
> >>> count <= count + 1;
> >>> end
> >>> end
> >>>
> >>> endmodule
> >> I have a minimal knowledge of Verilog and may be wrong but...
> >
> > I am not a Verilog expert either (use VHDL exclusively), but to me
> > the code of Robert Finch looks o.k from the HDL perspective
> > (functionality is something else, I addressed it in my replay
> > below). His Verilog appears to be an exact equivalent of VHDL code
> > below, which is perfectly legal synthesizable code under VHDL-2008
> > rules.
> >
> >
> > library ieee;
> > use ieee.std_logic_1164.all;
> > use ieee.numeric_std.all;
> >
> > entity Collatz_conjecture is
> > port (
> > rst : in boolean;
> > clk : in std_logic;
> > startn : in unsigned(127 downto 0);
> > count : out unsigned(127 downto 0);
> > done : out boolean
> > );
> > end entity Collatz_conjecture;
> >
> > architecture a of Collatz_conjecture is
> > signal n : unsigned(127 downto 0);
> > begin
> > process (clk)
> > begin
> > if rising_edge(clk) then
> > if rst then
> > n <= startn;
> > count <= (others => '0');
> > done <= false;
> > elsif not done then
> > if n(0)='0' then
> > n <= '0' & n(n'high downto 1);
> > else
> > n <= n+n+n+1;
> > end if;
> >
> > if n < startn then
> > done <= true;
> > end if;
> >
> > count <= count + 1;
> > end if;
> > end if;
> > end process;
> > end architecture a;
> >
> >
>
> Well then I just don't get this at all.
> I have a VHDL textbook that explicitly states that IN ports are input
> only, OUT ports are output only, and INOUT are input and output
> (tri-state).
>
Sounds like old textbook, not updated with VHDL-2008 changes related to
what is legal for 'out' ports.
See, for example, here:
https://docs.amd.com/r/en-US/ug901-vivado-synthesis/Reading-Output-Ports
--- SoupGate-Win32 v1.05
* Origin: you cannot sedate... all the things you hate (1:229/2)
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