From: ThatWouldBeTelling@thevillage.com   
      
   Michael S wrote:   
   > On Sat, 21 Feb 2026 15:39:42 -0500   
   > EricP  wrote:   
   >   
   >> Robert Finch wrote:   
   >>> On 2026-02-19 5:10 a.m., Michael S wrote:   
   >>>   
   >>>> If it is smaller than Kintex KU5P then I'd strongly suspect that   
   >>>> you didn't clean out all mistakes.   
   >>>>   
   >>>>   
   >>>>   
   >>> There could be more mistakes for sure. But I am sure the lowest   
   >>> level core works. It seemed to in simulation. I made a slight mod   
   >>> to it since I tested it last, checking n < startn.   
   >>> Counts are not used so the logic would be stripped out, but its   
   >>> good for verification.   
   >>>   
   >>> 1 Core is:   
   >>>   
   >>> module Collatz_conjecture(rst, clk, startn, count, done);   
   >>> input rst;   
   >>> input clk;   
   >>> input [127:0] startn;   
   >>> output reg [127:0] count;   
   >>> output reg done;   
   >>> reg [127:0] n;   
   >>>   
   >>> always_ff @(posedge clk)   
   >>> if (rst) begin   
   >>>     n <= startn;   
   >>>     count <= 0;   
   >>>     done <= FALSE;   
   >>> end   
   >>> else begin   
   >>>     if (!done) begin   
   >>>         if (~n[0])   
   >>>             n <= n >> 2'd1;   
   >>>         else   
   >>>             n <= n+n+n+1;   
   >>>         if (n < startn)   
   >>>             done <= TRUE;   
   >>>         count <= count + 1;   
   >>>     end   
   >>> end   
   >>>   
   >>> endmodule   
   >> I have a minimal knowledge of Verilog and may be wrong but...   
   >   
   > I am not a Verilog expert either (use VHDL exclusively), but to me the   
   > code of Robert Finch looks o.k from the HDL perspective (functionality   
   > is something else, I addressed it in my replay below).   
   > His Verilog appears to be an exact equivalent of VHDL code below,   
   > which is perfectly legal synthesizable code under VHDL-2008 rules.   
   >   
   >   
   > library ieee;   
   > use ieee.std_logic_1164.all;   
   > use ieee.numeric_std.all;   
   >   
   > entity Collatz_conjecture is   
   >  port (   
   >   rst    : in  boolean;   
   >   clk    : in  std_logic;   
   >   startn : in  unsigned(127 downto 0);   
   >   count  : out unsigned(127 downto 0);   
   >   done   : out boolean   
   >  );   
   > end entity Collatz_conjecture;   
   >   
   > architecture a of Collatz_conjecture is   
   >  signal n : unsigned(127 downto 0);   
   > begin   
   >  process (clk)   
   >  begin   
   >   if rising_edge(clk) then   
   >     if rst then   
   >       n <= startn;   
   >       count <= (others => '0');   
   >       done <= false;   
   >     elsif not done then   
   >       if n(0)='0' then   
   >         n <= '0' & n(n'high downto 1);   
   >       else   
   >         n <= n+n+n+1;   
   >       end if;   
   >   
   >       if n < startn then   
   >         done <= true;   
   >       end if;   
   >   
   >       count <= count + 1;   
   >     end if;   
   >   end if;   
   >  end process;   
   > end architecture a;   
   >   
   >   
      
   Well then I just don't get this at all.   
   I have a VHDL textbook that explicitly states that IN ports are input only,   
   OUT ports are output only, and INOUT are input and output (tri-state).   
      
   The language spec SystemVerilog IEEE_Std-1800-2017   
   (it's a horrid language - the spec is 1315 pages long,   
   and so complex that no compiler implements all of it,   
   and some compilers still use the pre-2005 language spec)   
      
   says in section "23.3.3.2 Port connection rules for variables" that   
   "Assignments to variables declared as input ports shall be illegal."   
   "Procedural or continuous assignments to a variable connected to the   
   output port of an instance shall be illegal."   
      
   but it also says "An output port can be connected to a net (or a   
   concatenation) of a compatible data type. In this case, multiple drivers   
   shall be permitted on the net"   
      
   and in "23.3.3.1 Port coercion   
   A port that is declared as input (output) but used as an output (input)   
   or inout may be coerced to inout. If not coerced to inout, a warning   
   shall be issued."   
      
   but never defines what "coerced" means or how to do it.   
      
   Verilog-2017 also has the "uwire" data type which is a uni-driver type   
   that only allows a single driver for the wire.   
   (But some compilers don't support uwire)   
      
   "6.6.2 Unresolved nets   
   The uwire net is an unresolved or unidriver wire and is used to model nets   
   that allow only a single driver. The uwire type can be used to enforce this   
   restriction. It shall be an error to connect any bit of a uwire net to more   
   than one driver. It shall be an error to connect a uwire net to a   
   bidirectional terminal of a bidirectional pass switch.   
      
   The port connection rule in 23.3.3.6 enforces this restriction across   
   the net hierarchy or shall issue a warning if not."   
      
   "23.3.3.6 Single source nets (uwire)   
   If the net on either side of a port has the net type uwire,   
   a warning shall be issued if the nets are not merged   
   into a single net, as described in 23.3.3.7."   
      
   and spec contradicts itself as to whether it is an error or warning.   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)