From: bc@nospicedham.freeuk.com   
      
   On 16/12/2017 17:40, James Van Buskirk wrote:   
   > "Bartc"  wrote in message news:zCaZB.23469$YE3.12688@fx06.am4...   
   >> On 27/08/2017 09:49, wolfgang kern wrote:   
   >   
   >> > [...about register names]   
   >   
   >> > you are free to decide and may rename all registers after girls,   
   >> > but I heavy daubt that this make your source better readable.   
   >   
   >> I've used alternate names via macros using Nasm.   
   >   
   >> I'm also in the middle of writing an x64 assembler designed for   
   >> working with the output of code generators, and there I use a similar   
   >> scheme.   
   >   
   >> Here's why: the names in my scheme are completely consistent, unlike   
   >> the Intel-style 'official' register names shown in brackets:   
   >   
   >> 64-bit        32-bit        16-bit        8-bit         Generic   
   >   
   >> D0  (rax)     A0  (eax)     W0  (ax)      B0  (al)      R0   
   >> D1  (rbx      A1  (ebx)     W1  (bx)      B1  (bl)      R1   
   >> D2  (rsi)     A2  (esi)     W2  (si)      B2  (sil)     R2   
   >> D3  (rdi)     A3  (edi)     W3  (di)      B3  (dil)     R3   
   >> D4  (r10)     A4  (r10d)    W4  (r10w)    B4  (r10l)    R4   
   >> D5  (r11)     A5  (r11d)    W5  (r11w)    B5  (r11l)    R5   
   >> D6  (r12)     A6  (r12d)    W6  (r12w)    B6  (r12l)    R6   
   >> D7  (r13)     A7  (r13d)    W7  (r13w)    B7  (r13l)    R7   
   >> D8  (r14)     A8  (r14d)    W8  (r14w)    B8  (r14l)    R8   
   >> D9  (r15)     A9  (r15d)    W9  (r15w)    B9  (r15l)    R9   
   >> D10 (rcx)     A10 (ecx)     W10 (cx)      B10 (cl)      R10   
   >> D11 (rdx)     A11 (edx)     W11 (dx)      B11 (dl)      R11   
   >> D12 (r8)      A12 (r8d)     W12 (r8w)     B12 (r8l)     R12   
   >> D13 (r9)      A13 (r9d)     W13 (r9w)     B13 (r9l)     R13   
   >> D14 (rbp)     A14 (ebp)     W14 (bp)      B14 (bpl)     R14   
   >> D15 (rsp)     A15 (esp)     W15 (sp)      B15 (spl)     R15   
   >   
   > Why is it preferable to use anything other than the architected   
   > register numbers?   
      
   Because they're a mess. Here are the regular set (expressed as 64-bit   
   versions), and ordered by internal code 0..15 where the top bit is one   
   of the REX bits:   
      
   rax   
   rcx      Win64 parameter passing, parameter 1   
   rdx      Win64 param 2   
   rbx   
   rsp      Stack pointer   
   rbp      Frame pointer   
   rsi   
   rdi   
   r8       Win64 param 3   
   r9       Win64 param 4   
   r10   
   r11   
   r12   
   r13   
   r14   
   r15   
      
   The reserved registers for stack and frame pointers (where the latter is   
   used) and parameter passing registers are in arbitrary places making it   
   harder to allocate registers for actual coding.   
      
   In my scheme, all D0-D9 are available; parameters are passed in D10-D13,   
   and frame/stack are D14/D15.   
      
   However, I still need to bear in mind the special registers, such as rdx   
   paired with rax (D11/D0), and parts of rcx used as a count (D10).   
      
   Although this is still a nuisance even using the official registers, as   
   rcx and rdx also have a role in parameter passing: you can't load the   
   first two arguments, then do a multiply that requires rdx:rax for the   
   third. Or keep a parameter in rcx while trying to do a variable shift.   
      
     The above numbering doesn't reflect the   
   > overlap between RBP and R13 or RSP and R12.   
      
   What overlap is that: that the bottom 3 bits of the register code? And   
   why is it important, as all bottom 8 registers will 'overlap' with the   
   top 8?   
      
      
   --   
   bartc   
      
   --- SoupGate-Win32 v1.05   
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