From: bc@nospicedham.freeuk.com   
      
   On 17/12/2017 07:43, Rod Pemberton wrote:   
   > On Sat, 16 Dec 2017 15:05:42 +0000   
   > Bartc  wrote:   
   >   
   >> Here's why: the names in my scheme are completely consistent, unlike   
   >> the Intel-style 'official' register names shown in brackets:   
   >>   
   >>   
   >> 64-bit        32-bit        16-bit        8-bit         Generic   
   >>   
   >> D0  (rax)     A0  (eax)     W0  (ax)      B0  (al)      R0   
   >> [...]   
   >   
   > If B stands for Byte, and W stands for Word, what do A and D stand for?   
      
      
   A for accumulator I think, and D for double. (I preferred not to use R   
   as R8-R15 will clash with existing Intel registers. Or rather AMD   
   registers as  I think they invented x64)   
      
   > Byte, Word, Double-word, and Quad are semi-standard names for 8-bits,   
   > 16-bits, 32-bit, and 64-bit respectively, yes?  Not only would the   
   > names be consistent using B W Q D but they would also indicate the size   
   > of the argument as well.   
   >   
   >    Q0            D0            W0            B0   
   >    Q1            D1            W1            B1   
   > ...   
      
   Yes, that's another way of doing it.   
      
   I'm mainly doing code generating, or using inline code, for a language   
   where 'word' is 32 bits and 'dword' is 64 bits. So I didn't want to   
   create too much confusion. 16- and 8-bit registers are little used so   
   using W and B for those is OK.   
      
   (My new assembler still uses O, Q, D, W, B for instruction opcodes and   
   size overrides, so is at odds when the register naming. The reason is   
   that would have been a massive job, when using Nasm, to rename all that   
   with macros. Also I would have had to think of a new prefix to mean 16-bit.)   
      
   --   
   Bartc   
      
   --- SoupGate-Win32 v1.05   
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