From: james.harris.1@nospicedham.gmail.com   
      
   On 06/04/2019 00:38, Edward Brekelbaum wrote:   
   > In ring 3, you'll seg fault.   
      
   That's if running under an OS, presumably. But I guess it would be   
   different if running on a bare machine (the case in point) where valid   
   memory address ranges have not been set up in GDT/LDT or page tables.   
      
   >   
   > In ring 0, you should get all ones (IIRC). The transaction goes down the ISA   
   bus and times out.   
      
   For some reason I, too, would most expect a read would get all ones   
   back, but I am not sure why. Perhaps it's based on the idea of a bus   
   which is carried off a computer by an edge connector. In such a case   
   IIRC computers used pull-up resistors on bus lines to provide signal   
   stability. Any line which was to be read as zero had to be driven low.   
      
   >   
   > My knowledge is pretty dated. It's possible chipsets that have dropped   
   support for ISA will behave differently.   
      
   Agreed. I may be thinking of how old ISA buses were configured. Perhaps   
   it's even possible that the MCH (term?) would direct different addresses   
   to different buses such that some addresses which had no RAM or device   
   at the end of them would return zeroes and others would return ones.   
      
   >   
   > Those addresses should resolve to uncacheable, so there will be a pretty   
   hefty performance penalty in any case.   
   >   
      
   Again, only if ranges have been defined (in MTRRs, in this case). That   
   said, perhaps MTRRs are set up by the BIOS rather than leaving them to   
   the operating system.   
      
      
   --   
   James Harris   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)