From: nowhere@nospicedham.never.at   
      
   On 08.08.2021 12:03, wolfgang kern wrote:   
   > On 07.08.2021 17:51, R.Wieser wrote:   
   > ...   
   >> and for some reason I can't get the FXSAVE to work (my assembler shows   
   >> its   
   >> age by not knowing the opcode, and trying to use a "db 0Fh,0AEH, ....."   
   >> sequence crashes the program).   
   >   
   > on older CPUs  0F AE xx will raise exception 6 [illegal opcode] if:   
   >   
   > 1) bit 5 of xx is 1  (xx 20..3F, 60..7F, A0..BF)   
   >    newer CPU may show a few valid instructions (see sandpile.org)   
   >   
   > 2) mod=3 aka register operand (C0..FF) [memory only!]   
   >   
   > 3) may raise EXC_6 if not supported   
   >     0F AE 90..97 98..9f  mean STMXCSR LDMXCSR [support specific]   
   >   
   > so I'd recommend either   
   >     0F AE 06 00 xx  FXSAVE [xx00h]  (needs 512 byte DS: buffer !)   
   > or shorter   
   >     0F AE 00        FXSAVE [bx+si]  (ditto)   
   > or HLL styled :)   
   >     0F AE 46 00     FXSAVE [bp+0]   (needs 512 byte on SS: stack)   
      
   you seem to work with 32 bit:   
      
   0F AE 07   FXSAVE [edi]   
      
   you used 27, so I were confused and had you look at my AMD docs,   
   it says: FXSAVE mem512env 0F AE /0   this Zero means bits 3..5   
   and I also checked on sandpile.org.   
   0F AE /4  means XSAVE (it's for CPU status and  not for the FPU)   
   __   
   wolfgang   
      
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