From: mutazilah@nospicedham.gmail.com   
      
   On Saturday, April 15, 2023 at 10:36:37 PM UTC+8, Paul Edwards wrote:   
      
   > I finally realized that since I'm getting an interrupt from    
   > the TBE enable (for unknown reasons), then if I moved    
   > the disable (cli) before that, then by the time I had    
   > outputted a byte, the interrupt would still be pending    
   > and even if I didn't get one for the outputted byte, it    
   > was enough to get one for the TBE call.    
   >    
   > And now it is working, with the simple design.   
      
   Note that it is working (and previously failing) under   
   Bochs. I haven't tried real hardware yet.   
      
   And now I realize there may be a problem with the   
   current code.   
      
   Let's say the serial port is slow.   
      
   The sequence I am doing is enabling TBE and then outputting   
   a byte.   
      
   Enabling TBE generates an interrupt, but outputting the byte   
   only randomly does (could also be a Bochs bug).   
      
   Because I am now relying on the TBE enable interrupt to get   
   me out of the HLT loop, I am no longer have the desired   
   constraint on the OUT instruction completing.   
      
   Meaning the second time through the loop, the second OUT   
   could be executed before the first one has completed.   
      
   If the UART discards the TBE interrupt when it realizes that   
   it is no longer the case that the transmit buffer is empty,   
   because there has been an OUT instruction issued since   
   then, then my current design should work.   
      
   Does anyone know what is happening?   
      
   Thanks. Paul.   
      
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