From: mr.neeraj@gmail.com   
      
   Also, the overheads of modulo scheduling can make it worse.   
   Overheads include, more registers, prolog and epilog instructions.   
   As Tim said, only advantage is in hiding latencies such as memory   
   access   
   and floating point.   
      
   =Neeraj   
      
   On Aug 29, 5:42 pm, Pertti Kellomaki  wrote:   
   > Tim Frink wrote:   
   > > My question was if also a significant performance increase for RISC   
   > > architectures with a restricted number of functional units can be   
   > > expected when software pipelining is applied.   
   >   
   > I'm not sure about significant increase, but it seems that even with   
   > a small number of FUs pipelining could be used to hide latency (e.g.   
   > memory  access). But if FUs are already busy without software   
   > pipelining, then pipelining is not going to make them any busier.   
      
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    * Origin: you cannot sedate... all the things you hate (1:229/2)