From: sidtouati@inria.fr   
      
   Neeraj Goel a icrit :   
      
   > Also, the overheads of modulo scheduling can make it worse.   
   > Overheads include, more registers, prolog and epilog instructions.   
   > As Tim said, only advantage is in hiding latencies such as memory   
   > access and floating point.   
      
   Software pipelining is usually beneficial for loops with a high number   
   of iterations.   
      
   S   
      
   ps: In order to hide memory latencies, non blocking caches should be   
   present in the underlying cpu. This is not common in vliw processors.   
      
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