XPost: comp.arch   
   From: gavin@allegro.com   
      
   In comp.arch Ray Dillinger  wrote:   
   > If I had my druthers, I'd add a number of VERY wide registers   
   > replacing on the chip die the "implicit" registers known as cache   
   > lines and make the management of these explicit with its own   
   > instructions rather than implicit and heuristic.   
      
   How many of such registers would you want? Making them explicitly   
   visible registers bulks up your context switch saved-state.   
      
   Or is there an opportunity to re-introduce instructions that operate   
   directly on memory and support large data types / SIMD that happen to   
   execute extremely efficiently if the operands match cache line   
   size and alignment?   
      
   G.   
      
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