0b751a3e   
   From: terekhov@web.de   
      
   SG wrote:   
   [...]   
   > on. As long as programmers have a vague idea of what a data race is,   
   > what they can do to avoid them (amotics, . . .   
      
   Yeah, right, 'amotics' ;-)   
      
   Lock-free atomics are inherently racy and the default memory model for   
   lock-free atomics shall be the most relaxed one, not sequentially   
   consistency (SC).   
      
   On PPC/POWER/PowerPC, for SC, you would need most heavy fence 'hwsync'   
   between each pair of SC lock-free atomic operations, there are examples   
   showing this for each pair: RR, RW, WR, and WW.   
      
   Lock-based atomics do not need 'hwsync' instruction but nobody needs   
   lock-based atomics because locking can be done more efficiently on   
   higher level.   
      
   regards,   
   alexander.   
      
      
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